Achieving cost-effective performance over time requires an organized, disciplined, and time-phased approach to product design, development, qualification, manufacture, and in-service management. Guidebook for Managing Silicon Chip Reliability examines the principal failure mechanisms associated with modern integrated circuits and describes common practices used to resolve them.
This quick reference on semiconductor reliability addresses the key question: How will the understanding of failure mechanisms affect the future?
Chapters discuss:
failure sites, operational loads, and failure mechanism
intrinsic device sensitivities
electromigration
hot carrier aging
time dependent dielectric breakdown
mechanical stress induced migration
alpha particle sensitivity
electrostatic discharge (ESD) and electrical overstress
latch-up
qualification
screening
guidelines for designing reliability
Guidebook for Managing Silicon Chip Reliability focuses on device failure and causes throughout - providing a thorough framework on how to model the mechanism, test for defects, and avoid and manage damage. It will serve as an exceptional resource for electrical engineers as well as mechanical engineers working in the field of electronic packaging.
Introduction How Devices Fail Intrinsic Mechanisms Extrinsic Mechanisms Intrinsic Device Sensitivities Device Transconductance Sensitivities Leakage Current Sensitivities Breakdown Issues Electromigration Description of the Mechanism Modeling of the Mechanism How to Detect/Test How to Manage Hot Carrier Aging Description of the Mechanism Modeling of the Mechanism Detection of Hot Carrier Aging Avoidance of Hot Carrier Aging Time Dependent Dielectric Breakdown Description of the Mechanism Modeling of the Mechanism How to Detect/Test How to Avoid and Manage Mechanical Stress Induced Migration Description of the Mechanism Modeling of the Mechanism How to Detect/Test How to Manage Alpha Particle Sensitivity Description of the Mechanism Modeling of the Mechanism Prevention of Alpha Particle Induced Damage Electrostatic Discharge and Electrical Overstress Description of the Mechanism Modeling of the Mechanism Avoiding ESD/EOS Failures Latch-Up Description of the Mechanism How to Detect How to Avoid Qualification Qualification Testing Virtual Qualification Screening Functional Tests Burn-In Tests Iddq Tests Design for Reliability Design System Effective Management of Wear-Out Failures Extrinsic Reliability Mechanisms Infant Mortality Failure Mechanisms Circuit Sensitivities Summary--此文字指其他 kindle_edition 版本。
![“Guidebook for Managing Silicon Chip Reliability (Electronic Packaging 5) (English Edition)”，作者：[Michael Pecht, Riko Radojcic, Gopal Rao]](https://images-cn.ssl-images-amazon.cn/images/I/41YAY8cOs1L._SY346_.jpg)
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